1. Field of the Invention
This invention relates to a method for electrically measuring the size of openings. More particularly, this invention relates to a method of electrically measuring the size of vias in an integrated circuit structure.
2. Description of the Related Art
In the fabrication of integrated circuit structures, the ever increasing density of devices, including the interconnects between devices, has resulted in the size of both the devices and their interconnects becoming smaller and smaller. This, in turn, has resulted in the need for high resolution photolithography to accurately position and construct devices and their interconnects on a substrate. As a result, lines of widths as small as 1 micron or less are now frequently employed in integrated circuit structures.
Accurate measurement of the width of such lines to verify the photolithography is difficult. For example, the use of scanning electron microscopy (SEM) is not always satisfactory because the edge of the line may be hard to define if the line becomes electrically charged.
More recently, measurement of the width of such fine lines has been made by electrical measurements. Test patterns of the same layer of conductive material are patterned on a wafer, including test patterns of lines of the same line width, i.e., laid out using the same photolithography. The sheet resistance of the conductive layer is determined and then a known current is passed along a line of known length and the voltage drop along the known length is measured. From these measurements, the width of the fine line may be accurately calculated.
While this technique has been successful in the measurement of line widths of fine lines used in VLSI integrated circuit structures, the measurement of the size of the vias or openings used for vertical interconnects between conductive layers has still has remained difficult. It would, therefore, be desirable to provide a technique where the size of such openings could be accurately monitored.